On: The first RISC-V portable computer is now availabl...

[RyJones]

Open source ISA - no licensing fees.

[LAC-Tech → RyJones]

What does that mean in practice - easier for people to manufacture hardware for them?

[alexisread → LAC-Tech]

You can get many open source soft cpus to run on FPGAs. The interesting bit is that RISCV is supposed to be extensible ie. it's easy to modify these cpus to provide interesting designs eg. Tagged memory to allow fast hybrid software/ hardware GCs, asynchronous cpus, rump cpus for DMA etc.

These new designs can then be used commercially- that's a big win for computing in general.

[RyJones → LAC-Tech]

Yes. You don’t need to sign up for a membership or some other thing to manufacture chips that comply with the standard.

[freemint → RyJones]

But it also means people are implementing modified ISAs (such as this CPU which has a non standard V extension) which sucks for compatibility.

[snvzz → freemint]

>But it also means people are implementing modified ISAs... which sucks for compatibility.

I've seen this a lot, both as misunderstanding and as FUD.

RISC-V was designed from the start with extensions in mind. This includes allocations for custom extensions that aren't standardized by RISC-V.

>(such as this CPU which has a non standard V extension)

There's nothing actually "incompatible" with this SoC, in the conflicting sense.

D1's V does naturally use these custom extension allocations and thus does not collide with the standard V.

It will therefore run RV64GC code just fine, and an illegal instruction exception will trigger should standard V code be encountered.