RISC-V requires less hardware complexity, and I think GigaDevice's GD32VF microcontrollers have gotten lower energy usage out of that (compared to the otherwise identical GD32F microcontrollers with an ARM Cortex-M core). I don't think it's especially easy to write compiler backends for, though I haven't tried yet; the instruction set is nice and small and orthogonal, yes, but most of the time the subset of instructions a compiler backend actually uses on amd64 or whatever is also nice and small and orthogonal. It's much easier to write emulators for, both because the instruction set is small and because, like the MIPS, it has no condition-code flags, a property that has caused consternation among GMP developers. And there is of course a much wider range of logic designs available for RISC-V than for any other architecture, because it's the first open-source architecture that's become popular.
For me one of the biggest draws is that the privileged spec is enormously simpler than the corresponding morass for most other architectures, especially i386 and amd64. Writing a toy, but working, virtual-memory operating-system kernel for RISC-V seems like the kind of thing you could do in a weekend rather than a semester. And that's enormously freeing.
Trouble is, almost all the actual physical RISC-V hardware I've seen so far seems to be microcontroller-oriented, so it doesn't have an MMU, so it doesn't support this stuff. SiFive has sold some boards called HiFive Unmatched and HiFive Unleashed with multi-core RISC-V CPUs they built that I'm pretty sure did have MMUs (since you could run Linux on them), but they're gone now (https://www.mouser.com/ProductDetail/SiFive/HF105-000?qs=zW3...).
So something like the Allwinner D1 seems really appealing. Just, not saddled with a keyboard that's both too big to fit in my pocket and too small to actually type on. The Clockwork Pi would be a good fit — but 64 MiB is pretty small for running modern Linux.
Some time after MIPS shot itself in the head by killing MIPS Open, it's nice to have a reasonably well designed and well-supported open architecture and instruction set.
edit: apparently there are open versions of SPARC and POWER, so... maybe there's not a lot of value in RISC-V except that it's simpler than the other two, drops irritating legacy features (register windows, condition codes...) and is in general designed for modern implementation?
You can get many open source soft cpus to run on FPGAs. The interesting bit is that RISCV is supposed to be extensible ie. it's easy to modify these cpus to provide interesting designs eg. Tagged memory to allow fast hybrid software/ hardware GCs, asynchronous cpus, rump cpus for DMA etc.
These new designs can then be used commercially- that's a big win for computing in general.
Easier to write compiler backends for? Faster? Simpler?