I've seen this a lot, both as misunderstanding and as FUD.
RISC-V was designed from the start with extensions in mind. This includes allocations for custom extensions that aren't standardized by RISC-V.
>(such as this CPU which has a non standard V extension)
There's nothing actually "incompatible" with this SoC, in the conflicting sense.
D1's V does naturally use these custom extension allocations and thus does not collide with the standard V.
It will therefore run RV64GC code just fine, and an illegal instruction exception will trigger should standard V code be encountered.
I've seen this a lot, both as misunderstanding and as FUD.
RISC-V was designed from the start with extensions in mind. This includes allocations for custom extensions that aren't standardized by RISC-V.
>(such as this CPU which has a non standard V extension)
There's nothing actually "incompatible" with this SoC, in the conflicting sense.
D1's V does naturally use these custom extension allocations and thus does not collide with the standard V.
It will therefore run RV64GC code just fine, and an illegal instruction exception will trigger should standard V code be encountered.