Update on STM

[wisesage5001]

http://morepypy.blogspot.com/2013/08/update-on-stm.html

[nn4]

Obligatory anti STM hype links:

http://queue.acm.org/detail.cfm?id=1454466 http://webcache.googleusercontent.com/search?q=cache:HhZcU_j...

Pretty much all the generalized (not functional) memory TM schemes with adequate performance rely on hardware acceleration. If your design doesn't support that your design is wrong.

[kazagistar]

Is there any plans to work hardware transactional memory into the mix?

[kingkilr → kazagistar]

Current HTM implementations limit the size of a transaction to the L1 cache, so for the time being, no.

[4buser → kingkilr]

Even new Intel Haswell's STM?

[sanxiyn → 4buser]

Yes, Intel TSX too has a limited transaction size.