On: How DRAM changed the world

[anticensor]

No, 7.5 to 9.75ns during the DDR4 rein (DDR4-4266), according to that page.

[rasz → anticensor]

DDR2-1066 CL4 is also 7.5ns to first data.

[anticensor → rasz]

But DDR2-1066 is worse in second and later accesses.

[rasz → anticensor]

Consequent accesses are measuring bus speed, not actual DRAM cell latency. At that point data is already loaded into a row of sense amplifiers.