Luke (author of Hazard3) provided some context regarding including the Hazard3 cores alongside the M33's:
> I can't compare the sizes of the two cores. The final die size would likely have been exactly the same with the Hazard3 removed, as std cell logic is compressible, and there is some rounding on the die dimensions due to constraints on the pad ring design. I can say that we taped out at a very high std cell utilisation and we might have saved a few grey hairs during final layout and STA by deleting the RISC-V cores.
Their partners already have tons of alternative boards ready to go, including a few which are drop-in replacements for the Pico, if you don't mind spending a bit more for USB-C:
The problem is most of the boards from partners are specialized with different hardware add-ons and have a significant markup at about 10 USD a board, which makes it harder to justify buying a handful of boards to tinker with. It's quite unfortunate.
No, these are microcontrollers. They're the thing you'd put inside a device that needs a tiny bit of smarts, like Raspberry Pi's debug probe[0]. The case I have for my RPi5[1] uses an rp2040 to run the thermal management logic.
Oh, I was trying to understand why cheap chiniseum USB-C-powered products off Amazon were only charging from a cheap USB-A brick and not from my quality USB C chargers.
Ugh, that one was killing me the other day. I went through 3 different cables before I found a hardware designer on the company's discord who could explain the issue.
I suspect the microUSB would actually fail in OTG mode for the same reasons in that case though? It's the same thing in terms of needing extra resistors.
Probably so they can say that it's a drop-in upgrade over the Pico 1. It's not a drop-in upgrade if you have to redesign your project's case to use it.
No, it just needs 2 extra resistors to work properly, but will work as-is if you use USB-A to USB-C cables and as long as you don't pull more power than available by default (i.e. you can request 3A @ 5V just by adding two resistors, but without it you're limited to USB's defaults)
In the past, when usb-c just got introduced micro usb ports for significantly cheaper than usb-c, so it made some sense. Today, it makes no sense.
You can't request 3A via resistors and you don't need to. You can advertise being able to source 3A via resistors. The sink does not advertise how much power it draws (unless it speaks PD), sink's responsibility is to check for what the source advertises (either via resistors or PD) before attempting to draw more power than USB default if you want to be compliant, which boils down to a simple comparator/ADC reading.
Simple sinks just use two 5.1k resistors for pull-downs, no matter how much power they want to draw - and they always need these resistors (two for receptacles, one for plugs), otherwise they won't work with USB-C sources at all.
Indeed, that is a well-written technical book that one could read cover-to-cover. It has a clear progression of topics, and all of the text is beautifully written:
"Once secure boot is enabled, the bootrom verifies signatures of images from all supported media: flash, OTP, and images preloaded into SRAM via the UART and USB bootloaders. At this point you lose the ability to run unsigned images; during development you may find it more convenient to leave secure boot disabled. The next section describes the generation of signed images to run on a secure-boot-enabled device."
"The chip-level reset subsystem shares a register address space with other power management subsystems in the always-on domain. The address space is referred to as POWMAN elsewhere in this document. A complete list of POWMAN registers is provided in Section 6.4, “Power Management (POWMAN) Registers”, but information on registers associated with the brownout detector are repeated here."
"The clocks block provides independent clocks to on-chip and external components. It takes inputs from a variety of
clock sources, allowing the user to trade off performance against cost, board area and power consumption. From these
sources it uses multiple clock generators to provide the required clocks. This architecture allows the user flexibility to
start and stop clocks independently and to vary some clock frequencies whilst maintaining others at their optimum
frequencies."
Wow, this seems to address every complaint about the RP2040 I had. Be sure to read all the way to the bottom for the "One more thing" section. You can choose Cortex-M33 or RISC-V at boot time transparently!
For a mass produced product, why waste die space on RISC-V cores that can only be used instead of the Cortex cores? Why not just use that die space for more ram or another ARM core? Doesn't it make sense to sell a variant that is entirely RISC-V?
Supposedly it didn’t require any measurable amount of additional die space, because other things constrained the minimum size of the die (like the I/O pads), according to one of the Raspberry Pi engineers.
An additional ARM core would have required significant changes to the crossbar. Right now, only two cores can be active, not three.
It just means that the die already had to be large enough to physically fit the number of pin pads that they wanted to have. It doesn’t really say anything about the RISC-V cores. They could be big or small. But these do seem to be almost as powerful as the ARM cores, based on what people have said. (I still want to see more benchmarks.)
If I were to guess, they probably concluded that `cumulative wasted manufacturing cost` < `engineering fees and costs of maintaining two entirely different chips`.
I think this type of pseudo-wasteful design is not unheard of when manufacturer had two markets to deliver to that had substantially different processing, but not I/O, requirements, as well as when some of major features in already manufactured chip didn't work out and ways to offset losses would be nice.
Wild-ass guess; but I assume there is a lot of overlap in the functionality between the type of cores which would mean only a small amount of extra space is required for the additional RISC-V instruction set support as opposed to having distinct CPU cores.
It's very unlikely IMHO. Both the RISC-V and the M33 are very tiny in die area, compared to for example the 512kB RAM, or even compared to a few bond-pads.
Making a single core with two instruction decoders but a shared register file, caches, prediction logic and ALU would make sense for a very high-end application processor type core, but not for these small devices. You would also need an instruction set license from ARM for that, vs just licensing the M33 netlist.
Maybe a good place to ask this: does anyone know of an all-in-one board for battery management in small mobile devices? Recently started playing with the ESP32 and was surprised there isn't a ready-to-go board on AliExpress for handling usb battery charging with simultaneous device powering. I want to add a LiPo to my design and have it just work like my cell phone does.
Adafruit has a couple of LiPo charger boards, but they don't have the integration you'd want: you'd need a separate USB cable for charging.
ISTR that some of their ESP32 boards do, though. i.e., charge LiPo through the USB port.
Also, I think some of the Heltec boards do. I have one here with a JST battery connector, but I haven't used it in so long, I'm not sure. I think this is the one I have: https://heltec.org/project/wifi-kit32-v3/
Though I'll also not I'm having some problems getting it to take an upload properly, but I tend to find most of the LILYGO stuff takes a little experimentation to get everything right, then it is reliable once you know what it likes.
ESP32 chips supposedly has an integrated BMS, and it's used in M5Stack as well as Seeeduino XIAO. Weird part is it's not clearly stated how it works other than you're supposed to solder a battery on.
I'm currently exploring 2-cell solutions: BQ25886, BG25887, MP5461, MP2672, LTC3118, MP2639C, IP2326, BQ294533, MCP73213. And here are some single cell solutions: IP2312, ETA9740, TP5100, IP5328P, MCP73834, MCP73833, LTC1734, LTC4121.
I found some modules on aliexpress with usbc connector, for example:
Looks like it's an "and" in silicon and an "or" at boot time?
>RP2350 includes a pair of open-hardware Hazard3 RISC-V cores which can be substituted at boot time for the Cortex-M33 cores. Our boot ROM can even auto-detect the architecture for which a second-stage binary has been built and reboot the chip into the appropriate mode
So we've seen people discuss doing dirty tricks like trapping and emulating writes, among other horrible things, to get external RAM "working" on an RP2040. The RP2350 datasheet says it supports read/write memory mapping on its new QSPI memory interface. So, does that mean one can just straightforwardly hook up PSRAM? I'm not much of a hardware person but this seems very promising. (And also, I'm really curious how much better the performance will be if you can do that.)
Oh I see. I either got merged into this discussion from another thread or came here from a dupe link, but I was looking at the product page which didn't seem to talk about it.
How many of us here who frequent these forums are guilty of being irresponsible with digital waste/footprint when it comes to things like this?
The amount of different variations of Raspberry Pi's I've been collecting over the years for no good reason, all doing nothing. And I don't even consider myself part of the upper echelon/extremists when it comes to this.
With that said, I wonder when we will get Raspberry Pi Pico 2 W (with wireless/Bluetooth capabilites)
> The unique dual-core, dual-architecture capability of RP2350 provides a pair of industry-standard Arm Cortex-M33 cores, and a pair of open-hardware Hazard3 RISC-V cores, selectable in software or by programming the on-chip OTP memory.
Let’s do some math to see if this qualifies as something to worry about. They say they’ve sold 4 million Picos. The packaging can get recycled, but let’s just assume every single Pico ends up in a landfill. How big a problem is that?
Datasheets say they’re 21x51mm. Looks like they’re on the order of 5mm deep. So 5.35mL per Pico.
Four million of these would be 5659 gallons of Picos, 756 cubic feet.
So you could take the e-waste of every Pico sold to date, and put it in a single 9.1ft cube in your garage.
I’d argue that this doesn’t qualify as something we shouldn’t spend time worrying about. There’s probably at least one Pico, maybe running a sign at some EPA office, doing more good for the environment than all the waste from all of them together is causing harm.
The packaging and production waste is probably the bigger issue considering the efficacy of recycling and the knowledge that all the waste of production winds up in the Pacific ocean.
Yes and no. On the one hand, fixing those processes is a much bigger impact, you're 100% correct. But on the other hand, I as an individual can do exactly nothing to affect it. While my personal environmental impact is much smaller, I actually can control it. So both are valuable to think about in different ways.
Or do both? No one is telling you not to buy something you will use, but the OP was commenting about boards they purchased and never or rarely used. Being slightly more considerate about your use is free, and if more people do it, maybe it will move the needle a point or two.
> How many of us here who frequent these forums are guilty of being irresponsible with digital waste/footprint when it comes to things like this?
Literally everyone in the developed world is guilty of being irresponsible with digital waste/footprint.
If you already have any kids at all (for example), there's nothing you can do to reduce your damage to the earth. Go ahead and as many raspberry pis as will fit in your junk drawer and don't give it a second thought.
If you ever get on a plane for vacation, same story. Raspberry Pi is a rounding error.
If you buy a new phone every few years, again same story.
> If you already have any kids at all (for example), there's nothing you can do to reduce your damage to the earth
This is a misanthropic perspective, we should have no kids and die out to reduce ‘damage to the earth’. Best environmentalist is a mass murderer. Worst climate criminal is a sperm donor.
But if you look at the physical world, Earth already had 6 mass extinction events, asteroids, supervolcanoes, etc. they killed basically everything, and life bounces back. There will be more. Our efforts are unimpressive in comparison. In absolute, it doesn’t matter.
From a humanist view, ‘Damage to the earth’ is damage to its ability to support human life. That’s the perspective that makes sense to me.
One of the requirements is that civilisation continues.
And the best contribution is to bring up a well adjusted, kind and capable individual, and for them to do the same.
If lump together environmental impact of children and parents, then if your bloodline continues forever your evrironmental impact is infinite. This creative accounting leads to absurd conclusions
He didn't say that one shouldn't have kids due to environmental impact, he was just putting it in perspective. The point was that if you have kids, and if you don't worry about the environmental impact they cause, then you shouldn't worry about the much smaller impact of a Raspberry Pi either.
There's no need to keep the population growing as it is though. That's unsustainable. It's not all or nothing: make as many kids as possible or go extinct. There's a middle road.
It would be great if humanity would shrink to 1 or 2 billion. More than enough. Resources wouldn't be as scarce, housing wouldn't be a problem. Much less need for wars as most of those are driven by resource and land scarcity. It would be much easier to reach an equilibrium with nature.
The problem is that a high birth rate is viewed as a virtue due to religious and short-term budget concerns (more people to pay for pensions etc). While it's true that a shrinking humanity would cause temporary issues, it would only be for a while until it stabilises.
I for one am really happy with my decision of not having any kids.
I don't frown on people with 1 or 2 kids but I do on those with huge families. But that's just me, they are free to do so of course.
I said if you have kids don't hand wring over your environmental impact. It's like thinking that if you cry at the beach you're making the ocean saltier.
If you have kids you're betting that, "the best contribution is to bring up a well adjusted, kind and capable individual, and for them to do the same."
> How many of us here who frequent these forums are guilty of being irresponsible with digital waste/footprint when it comes to things like this?
Did you consider used market? I was stupid enough to not take the opportunity to make some good money when even ancient ones were unobtanium and overpriced everywhere, but recently managed to sell all my older ones at a decent price, so no direct waste was produced.
What concerns me more about this Pico however is the signed boot locking feature that if not reversible could lock a Pico to the original program forever, so an used one couldn't be repurposed for anything else even if a non malicious user wanted to reflash it entirely without reading the original content. I'm not sure about that so I'd welcome more information on the subject: could signed boot locking be reversed with a complete flash erase?
The used market is really good now from a buyers perspective. I'm working on a few projects and wanted a few extra pi's. Managed to grab a few used ones from people that have sidelined their projects. Good condition. Basically paid retail price but also got 7inch touch screens with each pi for free.
As tempting as a new toy may be, we are always welcome to put off getting new ones until we have made good use of the old ones. That is especially true of microcontrollers and development boards, where the need to upgrade is dictated by the needs of the project. This isn't like a computer or mobile device where anything from updates to end-user applications or the operating system will artificially obsolete them.
Semiconductor fabrication is nasty. It's way worse than most plastic production. Even the board substrate itself is probably the most toxic kind of plastic out there (other than maybe styrene feed stock) before its cured and being a composite it decomposes the slowest. It's much much worse than most household waste.
There are bigger things that produce way more waste though. Lots of vehicles (especially boats) have huge fiberglass composite components for example.
Woah an on-chip switch mode power supply? How does that work? I've put together these before on a PCB and they require an inductor and a bunch of other supporting passive elements. How does all that fit onto a chip?
If I read the datasheet correctly you still need an inductor and some passive components externally.
The only thing that is not needed is an external switch mode power supply chip.
Edit: reading further in that section of the data sheet, "The RP2350 has an on-chip switching regulator that powers the digital core at 1.1V (nominal) from the 3.3V supply,
which is not shown in Figure 7."
It has proven difficult enough to find a PDF of the schematic (I don't have Cadence Allegro installed) that I am giving up.
Lots of nice steady improvements but 8 high speed outputs is a really nice benefit.
> The maximum frequency for the HSTX clock is 150 MHz, the same as the system clock. With DDR output operation, this
is a maximum data rate of 300 Mb/s per pin.
Sounds like it is an approximately 9.5-bit ADC now, instead of 9-bit like the RP2040 was. So... not much change.
Datasheet section 12.4.1 "Changes from RP2040"
- Removed spikes in differential nonlinearity at codes 0x200, 0x600, 0xa00 and 0xe00, as documented by erratum RP2040-E11, improving the ADC’s precision by around 0.5 ENOB.
- Increased the number of external ADC input channels from 4 to 8 channels, in the QFN-80 package only.
I'm a bit surprised by the RISC-V cores. I thought the ARM investment would kill any such aspirations.
The investment was made nine months ago. Is a hardware design locked in at this point? We will see what happens in the future and whether we will get more RISC-V cores.
I honestly would've expected WiFi on-chip. There are fewer and fewer use cases without connectivity, and it's so wasteful to have a separate chip for that.
That functionality is absolutely non-trivial. There are a few WiFi cores (digital and RF) you can license but they are expensive and the analog part uses a lot of die area. If you look up die shots from the ESP chips, you see that the radio is more than half of the die.
Espressif apparently has their own WiFi implementation, which makes sense as they are a major vendor of very cheap tablet and cell phone WiFi radios. This is likely why they can offer that feature so cheaply.
There are tons of use cases for microcontrollers without wifi. The pico chip can and is used as a auxiliary micro to other systems that have networking already. The pico w will come out later this year.
You are mixing up SOCs and devboards. RP2040 is a chip, there has never been version with onboard communication.
Raspberry Pi Foundation released a RP2040 based dev board(Pico W) with an additional external wireless chip, as have others(including boards with an additional ESP32 just do comms).
>Before the end of the year, we expect to ship a wireless-enabled Pico 2 W, using the same Infineon 43439 modem as Pico W, and versions of both Pico 2 and Pico 2 W with pre-installed 0.1-inch headers.
So this may be a dumb question..
Why is a lot of ram needed for running a display? Is it just to be able to save all the pixel data? If you'd be generating your image on the fly then I'm assuming ram wouldn't matter because you wouldn't be storing anything?
800 * 480 * 16bit * 30fps = 23million bytes written out to the screen per second. Don't even look at higher resolutions, it's literally exponential in bandwidth. Video takes a lot of data. The highest resolutions and framerates put the fastest network speeds to shame.
A CPU just plain can't do this. Even if you want to pretend it's one cycle per pixel the realtime constraints at higher resolutions are way out of the realm of feasible. We struggle to do CPU driven audio in realtime as-is (Audio is measured in Khz of bandwidth rather than Mhz).
You can do this at very low resolutions easily enough (again it's exponential with resolution increase) but then you have a low resolution screen.
I worked with an ST Micro processor and small TFT display. The routine to write to the screen was to save the contents to RAM and then point a graphics renderer to that RAM. Double and triple buffering were required to avoid screen tearing (screen update with partial previous and next screen mixed.)
Is it just to be able to save all the pixel data. Intermeshing game logic processing with scanline generation is likely a bit too archaic for most projects.
The ESP32 is a fine series of MCUs, but it doesn't have PIOs, a choice between ARM and RISC-V (or both!), 5v-tolerant IO -- to name a few things that this new RP2350 provides.
There's a ton of stuff in the world that uses an MCU and doesn't have wireless, and that would not benefit from having wireless.
But if RP2350 features and wireless are both necessary today, then nothing but a few schekels and some space on the board stops anyone from integrating those things. One can have both.
Remember, even the ESP8266 was first seen in English-speaking DIY circles as just a way to add wifi to things like Arduino projects and not so much as a capable, programmable MCU itself.
There’s multiple people saying this so I’ll just ask politely. Every esp has a multitude of gpios. The esp8266 mentioned is almost entirely gpios on its pin out. I’ve used these extensively and it’s great for flexibility. From led indicators to full on activating a relay.
You say it’s not the same as the pi’s pios. So I’ll ask. What does the pi do here that the esp doesn’t?
The PIOs are state machines that let you develop custom peripherals that run asynchronously, not taking up CPU time. You could probably bitbang some custom peripherals on an ESP32/ESP8266, but that takes up a lot of CPU time and power.
The RP-series PIOs are little programmable IO controllers. They can do can do their own thing, running independently of the software running on the MCU's CPU core, which allows them to work in tight little loops with very precise and predictable timing.
People use PIOs to do all kinds of things.
For instance, here is a method for using RP2040 PIO to produce VGA signals, using nothing but a Pi Pico, some jumper wires, and a few resistors on a breadboard: https://vanhunteradams.com/Pico/VGA/VGA.html
I myself have used RP2040 PIO to get a consistent PWM output in what was a bit of a boondoggle. I was working in Micropython, and the documentation for that said it supported hardware PWM output on this hardware, but that output was affected by the code in my main loop and was glitchy in ways that I found to be unusable. Rather than investigate the apparent issue with Micropython, I instead put together a thing in RP2040 PIO assembler that produced adjustable PWM with absolutely perfect consistency regardless of whatever I was doing in software.
And at least in my own example: The performance hit of doing this was zero since PIO is a dedicated hardware block that handles jobs like this in any way that I can program up.
Now, sure: I'd rather have used hardware PWM because that's simpler for me. And the ESP32 does have hardware PWM. But that PWM block only does PWM -- it can't be adjusted to do other things, whereas the RP-series PIOs can run arbitrary code to handle IO tasks. (So why didn't I pick an ESP, instead? That's easy enough to explain: I already had a Pi Pico in-hand.)
---
Meanwhile, as a general construct: There is absolutely zero reason to fanboy one MCU platform over another. It is absolutely OK that there are multiple competing inexpensive DIY-friendly-ish things in this space. This isn't Highlander. This isn't the fucking Super Bowl or the World Cup. There can be more than one.
You're missing something but it's actually easy to get confused about.
GPIO: general purpose input/output. A pin that can be used by the main CPU core(s) to interrogate the outside world.
PIO: programmable input-output. A small, I/O dedicated state-machine that can be custom-programmed in a minimal assembly language to handle I/O tasks/simple protocols/state management, over GPIO/I2C/SPI etc., without taxing the primary CPU.
Some microcontrollers have basic features a little similar, but it's something the RP series is taking a lot more seriously than most. The RP2040 has eight of these PIO state machines; the RP2350 has 12.
There are some astonishing examples of what these things can do. But basically think of these as delegated GPIO/SPI/I2C etc. co-processors that can blaze away at high speeds on I/O tasks without needing the main cores until something "high-level" occurs.
Makes sense. I’ve worked a lot with multipurpose gpio that can also be configured as spi or i2c but this is another step beyond that. Thanks to everyone for this!
Which Raspberry Pi would one need to run Vim and Firefox? And is it possible to have it use a tablet as a monitor and draw power from it?
That would be everything I need to develop web applications. I wonder if I could use a 3-piece setup to do so:
A keyboard connected to the Pi
The Pi connected to a tablet which acts as a monitor
Not sure how much the Pi weights, probably less than 100g? The Apple Magic Keyboard for example is 230g. And the Lenovo Tab P12 for example is 570g. So together less than 1kg. For a Linux development machine with external keyboard, that would be quite nice.
Do yourself a favor and do not use a Pi for web development, it's way too slow for that. I knew that the Pi was slow when I got myself one (Pi 400) but I didn't think it would be THAT slow. Returned it the next day, barely usable. Better to only use a Pi for non-graphical stuff.
PI is in an interesting spot. For those who want cheap compute, a low end mini PC can deliver 5x the performance for 1.5x the price with more peripherals available while remaining portable. So it really only makes sense if you care about the form factor, power consumption or GPIO.
I use my PIs for basically two reasons - they can be conveniently powered from a USB hub and they can act as USB gadgets.
Any of the non-Pico Pis could do that although the highest performance would be one of the new Raspberry Pi 5 8GBs. The Pico series are not suitable for desktop computing
My dream is to have a device about the form factor of a Flipper Zero (with the same buttons) that I can then plug into a e-ink monitor and mechanical keyboard to turn it into a text editor.
I have built a few prototypes with Raspberry Pi Zeros, which are luxurious web servers -- 512mb of ram, capable of utilizing a 2tb sd card.
> I can't compare the sizes of the two cores. The final die size would likely have been exactly the same with the Hazard3 removed, as std cell logic is compressible, and there is some rounding on the die dimensions due to constraints on the pad ring design. I can say that we taped out at a very high std cell utilisation and we might have saved a few grey hairs during final layout and STA by deleting the RISC-V cores.
https://x.com/wren6991/status/1821582405188350417