On: Verilog Simulation with Verilator and SDL

[NextHendrix]

SystemVerilog and UVM are perfectly capable of being used to verify VHDL designs.

I should also add that if you wanted to use a single language for everything OSVVM is excellent.

[artisanspam → NextHendrix]

Sure it's capable, but there's certainly a cost of having to use multiple languages in your test bench/DUT. I'd argue that's one of the reasons why Verilator, CocoTB, Chisel, etc. haven't taken off in the "traditional" semiconductor industry (i.e. not FPGAs).