While Verilog is not SystemVerilog, it’s more or less a subset of it. And SystemVerilog had much more industry support for design verification. So if I were to design some open source software for HDLs, that reason alone would make VHDL a non-starter.
Sure it's capable, but there's certainly a cost of having to use multiple languages in your test bench/DUT. I'd argue that's one of the reasons why Verilator, CocoTB, Chisel, etc. haven't taken off in the "traditional" semiconductor industry (i.e. not FPGAs).