Measuring gate width also stopped being relevant. Densities continue to increase, and significantly so, despite gate-width staying relatively constant.
A 45nm process:
i7-880, 45nm
774 million transistors
296 mm2
A "14nm" process:
i7-6700k, 14nm
1.75 billion transistors
122 mm²
That's still a huge increase in density. It no longer means what it used to, but the spirit of the definition is still very much alive.
It is a significant increase in density, but falls well short of the expectation. Density is somewhat hard to compare because it depends on the way the chip is laid out and the amount of cache vs logic, but if we go by the size of a single sram cell (containing 4 transistors) we can make a relatively fair comparison. In 90nm a sram cell was 1um^2 and in 7nm a ram cell is .027um^2, an increase in density of 37x.
The expected scaling is that transistor density should have scaled with gate length squared (since the structures are laid out in a 2-D grid, for example the 0.8um process used in the 8088 had a sram density of 120um^2, compared to 1um^2 squared for 90nm, a factor of 120x for a roughly 10 times smaller process), so one would have expected a 165x improvement moving from 90nm to 7nm.
Unsurprisingly, the missing factor of 5 is the same factor between the process node name ('7nm') and actual gate length (~35nm).
A 45nm process:
A "14nm" process: That's still a huge increase in density. It no longer means what it used to, but the spirit of the definition is still very much alive.