A poorly held secret in the semi industry is that transistors have stopped scaling at around 30nm - the practical limit of 193nm litho.
What has been scaling was the amount of free space in between them, metal layers, design rules, cell designs and such.
Before transistor scaling stalled, any process node shrink was an automatic performance gain without any side effects, but not so much after. Some designs may well be seeing net losses with process shrinks these days.
From 10nm on, higher density is actually hurting your performance, not adding it. For a process technologist, you have now to work on both performance, and density in parallel, and not solely on the last one thinking that gains in it will automatically translate into gains in performance.
So its a tricky business now to both squeeze more transistors into a design, and have a net gain from it.
What has been scaling was the amount of free space in between them, metal layers, design rules, cell designs and such.
Before transistor scaling stalled, any process node shrink was an automatic performance gain without any side effects, but not so much after. Some designs may well be seeing net losses with process shrinks these days.
From 10nm on, higher density is actually hurting your performance, not adding it. For a process technologist, you have now to work on both performance, and density in parallel, and not solely on the last one thinking that gains in it will automatically translate into gains in performance.
So its a tricky business now to both squeeze more transistors into a design, and have a net gain from it.