I thought there was two different uop ISAs on big x86 cores with two different purposes these days. One is pretty close to the original instructions, just decoded and fixed width (on AMD at least, this is what's in the uCode ROM). Then those are cracked to another ISA that the ROB knows about because instructions will cross functional unit boundaries.
So in say 'rol mem_addr, shift', your inner ISA would be cracked to something like.
ld reg_temp0, mem_addr
rol reg_temp0, shift
st reg_temp0, mem_addr
This is all hearsay though; I could have certainly misheard/misremembered.
So in say 'rol mem_addr, shift', your inner ISA would be cracked to something like.
This is all hearsay though; I could have certainly misheard/misremembered.