> Another story is how DMA in the x86 world is cache coherent (no need to use uncached memory or flush before starting an I/O operation- which I have to do it in ARM). This is awesome from a device driver writer's point of view and is the result of having to support old operating systems from the pre-cache days.
Nitpick: You mean "Sequentially consistent".
ARM is cache coherent, but NOT sequentially consistent. x86 is almost sequentially consistent (only a few obscure instructions here and there violate it).
x86 is not sequentially consistent. Its consistency model is Total Store Order (same as most SPARCs). The store buffer is architecturally visible and newer loads can be reordered above older stores. More formally, all CPUs agree on the order of remote stores but might see their own stores in a different order.
For example Dekker algorithm fails on x86 without explicit fences or explicitly sequentially consistent stores (all atomic RMW operations are sequentially consistent on x86).
edit: I think the OP really meant cache coherency; while all ARM CPUs in a system are in the same coherency domain, the IO space might be outside of it.
> edit: I think the OP really meant cache coherency; while all ARM CPUs in a system are in the same coherency domain, the IO space might be outside of it.
If that's the case, then I stand corrected. My understanding was that ARM was fully cache coherent, but it makes sense that I/O would be a different case all together.
to be clear: I do not know whether IO on ARM is cache coherent or not, I'm just pointing out that just because all CPUs are cache coherent it doesn't imply that peripherals on external buses must be as well.
I wasn't thinking of the I/O case when I typed up my post earlier. I was thinking CPU-to-CPU coherency. In which case, you are probably right on this front.
Nitpick: You mean "Sequentially consistent".
ARM is cache coherent, but NOT sequentially consistent. x86 is almost sequentially consistent (only a few obscure instructions here and there violate it).