On: MIPSfpga 2.0: A CPU architecture course that’s dif...

[nerpderp83]

Closed cores and encumbered instruction sets are a thing of the past. CPUs and instruction sets are close to being commodity. One can already roll performant general systems with FPGAs. As FPGAs get more logic blocks that are amenable to building higher clock rate soft CPUs the general purpose CPU will be out.

If someone is going to have a full stack hardware class, why not use an un-encumbered soft CPU, specifically RISC-V, of which there are multiple high quality implementations in a variety of languages.

[rwmj → nerpderp83]

One day perhaps, but today my £300 FPGA runs a single 64 bit RISC-V core at under 50 MHz, and has an awful & proprietary toolchain.

[infinite8s → rwmj]

If you are using your FPGA to run a RISC-V core then you are doing it wrong.