Hacker News new | past | comments | ask | show | jobs | submit login
MIPSfpga 2.0: A CPU architecture course that’s different from the rest (imgtec.com)
71 points by ingve on July 21, 2017 | hide | past | favorite | 17 comments



At least things have changed a little. A chap I know from school wrote a MIPS core for opencores & ended up on the receiving end of lawyers. http://brej.org/yellow_star/

Granted this was many moons ago, and they have to protect their IP.


It must have been either violating the last patent still active for unaligned access or plain old trademark violation. I don't know how these guys can get away with calling it a "MIPS" core either.


Imagination purchased MIPS Technologies 4 years ago for $100M so I think they have the rights to use the MIPS trademark.

https://www.imgtec.com/news/press-release/acquisition-of-mip...


The blog posting is about the use of an official MIPS core along with the second release of some teaching materials.


I initially interpreted this as a new CPU architecture. Nope, Intel has the IP around mixed general-purpose and reconfigurable computing architectures.

Regardless, awesome idea for a course. Provide the source code for a complex architecture and let the students hack it.


A bunch of people are saying on this project that the core should be open including the classwork. In the real world you don't have the ability for a Core to be open at all. Having a closed core with IP issues is probably more representative of the real world. It would be nice to have another class that you could take concurrently that would be the ying to this yang that would have an open core though. The best I could find about one with an open core is http://www.cl.cam.ac.uk/teaching/1617/P35/ which details the OpenRISC 1200 but I don't think it goes in depth.


People used to say things like this about OS Kernels


Um BSD existed with source code since before I can remember and I'm old and cranky...


The fact a thing exists doesn't stop people from denying its possibility.


... and now? Where is the course material? Where can I get the soft core?

I suggest you to look at RISC-V or OpenRISC 1200. It might not have the course material at the momnent, but the core is available. Help to create the teaching material based of this... ?


Yah, I'm really confused about why its OK to give the core to a professor to distribute to his students, but not ok, to just provide a click through to allow us folks not enrolled in a supported university to download it.

I'm sure I can dig around in the darker corners of the internet and find the code... So why not give it to me directly with a license to the effect, you can look at this all you want but you can't actually do anything with it...


> Since May 2015, over 600 universities around the world have licenced and downloaded the MIPSfpga core, the Getting Started Guide, and the lab exercises.

Seems pretty cool, but I'm just wondering, is there any reason the core must be licensed for them to profit on this? Or could the core be opened and just the coursework licensed?


They aren't doing this as a money making exercise. It's a way for them to get the MIPS architecture out in the open and have the next generation of engineers get familiar with it. I think the licensing is just a way for them to protect access to what is still monetisable IP while still making it available for teaching purposes.


> It's a way for them to get the MIPS architecture out in the open.

Most computer architecture courses of the last 25 years have already been based on MIPS (or any MIPS-like or -light adapted version for the course). That's because the MIPS ISA is simple, regular and elegant, and the original MIPS is a pipeline simple enough to be taught easily and nevertheless able to present most important problems and solutions that a CPU and a pipelined CPU may encounter.


Closed cores and encumbered instruction sets are a thing of the past. CPUs and instruction sets are close to being commodity. One can already roll performant general systems with FPGAs. As FPGAs get more logic blocks that are amenable to building higher clock rate soft CPUs the general purpose CPU will be out.

If someone is going to have a full stack hardware class, why not use an un-encumbered soft CPU, specifically RISC-V, of which there are multiple high quality implementations in a variety of languages.


One day perhaps, but today my £300 FPGA runs a single 64 bit RISC-V core at under 50 MHz, and has an awful & proprietary toolchain.


If you are using your FPGA to run a RISC-V core then you are doing it wrong.




Consider applying for YC's first-ever Fall batch! Applications are open till Aug 27.

Guidelines | FAQ | Lists | API | Security | Legal | Apply to YC | Contact

Search: