On: An open source Xilinx Spartan 6 miniPCIe development board

[Sanddancer]

Yes. Xilinx chips can do on-the-fly reconfiguration. So you can have your bootstrap loader and then either load a more complete firmware from the spi chip, or over pcie

[mng2 → Sanddancer]

I don't think it's supported for Spartan-6 though.

[Sanddancer → mng2]

It is as of ISE-12. Some people, in fact, have reversed the datastream and can do it live, automatically, in realtime https://vjordan.info/log/fpga/full-dynamic-partial-reconfigu...

[jeff_marshall → Sanddancer]

yeah, isn't that hard to get the basics by reading the docs and doing some basic experiments with explicit placement and examining the resulting bitstream.

When I looked at the encryption format for the virtex 5 series it was quicker to reverse engineer it than it was to find someone within Xilinx that could explain it (just basic bit/byte order, what's covered by encryption, etc).

At the end of the day, FPGA configuration logic is just another state machine ;)

[vardump → Sanddancer]

That looks very interesting, thanks!

[vardump → mng2]

So it's not possible to implement compliant PCIe interface together with some bigger block with this board?

[mng2 → vardump]

Not with official workflows at least, and even then, you would somehow have to keep the PCIe block up during reconfiguration for compliance. I think it would be difficult to reverse engineer to that level.

The easier thing to do would be to delay enumeration.