Right. Individual DRAM cells are much slower than the SRAM cells used in the rest of a chip's cache system but they're also much denser which is why they're used for main memory. But IBM found that for large last level caches the shorter wires enabled by size savings of eDRAM were enough to offset the slower cells leading to a faster cache overall.
My understanding is that performance is better mostly because the memory is so close to the CPU, just like traditional CPU cache levels.