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shortsightedsid
on Nov 1, 2014
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How L1 and L2 CPU caches work, and why they’re an ...
I'm not sure about ARMv8 but in ARMv7 SoCs the ARM Subsystem does not include L3. Plus each L1 is tied to each core.
ganzuul
on Nov 1, 2014
[–]
I believe this is a relevant source:
http://www.arm.com/products/system-ip/interconnect/corelink-...
The L3 cache is 'integrated', which I presume means it's different names for the same thing.
shortsightedsid
on Nov 2, 2014
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Ah! Thanks for sharing. It is for ARMv8 which I really need to read up on.
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