Depending on the context, your friend may be right.
Power dissipation in a CMOS gate is made up of two primary components: static leakage and dynamic losses. Dynamic losses are related to the "dissipation" capacitance (Cdiss or Cpd in CMOS datasheets) and the switching frequency. If you want to understand why, consider charging an RC circuit. How much energy is lost to the resistor and how much is stored in the capacitor at the end of charging? How does the selection of the resistor and capacitor value impact this ratio?
So for minimum dynamic loss you want to minimize Cdiss which involves making gates as small as possible. However, this makes the static leakage higher. So it may not be universally as simple as "a smaller process is lower power". For a system which spends most of it's time in sleep, or clocks slowly it may actually be better to eat the dynamic loss of a larger process in order to get the lower leakage, which is something I believe TI did with some of the FRAM '430 parts (but I can't find the link now).
Power dissipation in a CMOS gate is made up of two primary components: static leakage and dynamic losses. Dynamic losses are related to the "dissipation" capacitance (Cdiss or Cpd in CMOS datasheets) and the switching frequency. If you want to understand why, consider charging an RC circuit. How much energy is lost to the resistor and how much is stored in the capacitor at the end of charging? How does the selection of the resistor and capacitor value impact this ratio?
So for minimum dynamic loss you want to minimize Cdiss which involves making gates as small as possible. However, this makes the static leakage higher. So it may not be universally as simple as "a smaller process is lower power". For a system which spends most of it's time in sleep, or clocks slowly it may actually be better to eat the dynamic loss of a larger process in order to get the lower leakage, which is something I believe TI did with some of the FRAM '430 parts (but I can't find the link now).