Hm, what's with the legal disclaimer at the beginning and at the end? I know it's for when Intel "lost" the legal battle about AMD for how icc intentionally pessimises for non-Intel CPUs[1], but what does that have to do with gcc? Is this a poisoned gift to free software?
On a different note, I'm excited to see that AVX2 includes broadcasting. Maybe future iterations of g++ will be able to automatically speed up broadcasting operations in GNU Octave!
The scatter instructions seem interesting for handling Octave's complex arrays as laid out in memory, interleaving real and imaginary parts. This is essentially std::vector<std::complex> in C++. Matlab instead stores each complex part contiguously, essentially std::pair<std::vector<double>, std::vector<double>>.
I have a question: are these vector instructions inherently running in parallel? Do they get spread out over several cores? Sometimes I get the impression that fancy new vectorisations are losing the optimisation race in favour of new tricks to better parallelise. Is that what those conflict detection instructions are for? Is this automatic? Do we really have truly automatic vectorisation?
[1] Intel's excuse is that they cannot guarantee that non-Intel CPUs have the full instruction set, but this is so obviously a lie, as if AMD's architecture were some obscure, undocumented beast that requires the worst possible opcodes.
On a different note, I'm excited to see that AVX2 includes broadcasting. Maybe future iterations of g++ will be able to automatically speed up broadcasting operations in GNU Octave!
https://www.gnu.org/software/octave/doc/interpreter/Broadcas...
The scatter instructions seem interesting for handling Octave's complex arrays as laid out in memory, interleaving real and imaginary parts. This is essentially std::vector<std::complex> in C++. Matlab instead stores each complex part contiguously, essentially std::pair<std::vector<double>, std::vector<double>>.
I have a question: are these vector instructions inherently running in parallel? Do they get spread out over several cores? Sometimes I get the impression that fancy new vectorisations are losing the optimisation race in favour of new tricks to better parallelise. Is that what those conflict detection instructions are for? Is this automatic? Do we really have truly automatic vectorisation?
[1] Intel's excuse is that they cannot guarantee that non-Intel CPUs have the full instruction set, but this is so obviously a lie, as if AMD's architecture were some obscure, undocumented beast that requires the worst possible opcodes.