One thing I'm looking forward too more than the power saving advances are the arbitrary precision maths they are starting to finally add. Albeit just integer , add and multiply instructions for now, but a good start.
MULX was introduced on Haswell as part of the BMI instructions. Basically it allows two explicit destinations (still an implied rdx source though).
ADCX/ADOX are pretty weird. They both operate basically the same as ADC, but only read/write the carry or overflow flag respectively. The idea is to allow two interleaved independent chains of adds, putting less pressure on the out-of-order logic on chip. This seems kinda weird though: the renaming logic would have to detect that the bit of the flags register that one chain of adds reads aren't written by the other chain, so those instructions wouldn't be hazards, and thus both chains can be executed in parallel. OTOH, IIRC there are other instructions that only write certain bits of the flags, so I guess the logic for this bit-level renaming of flags is already there.
