1) Templates
2) SIMD, but also auto-vectorization. gcc/g++ do an OK job of using SSE instructions when they can. If you have a loop like:
for (int i = 0; i < 16; i++) {
vec[i] *= 16;
}
gcc can sometimes emit SIMD code for you, without having to think about it. If you need to go farther, it's easy to use something like ispc to write vectorized code and link it into your program. It's more work to take advantage of hyper-optimized C from Go.
Cache-optimized layouts: Not where it comes from, but things like forcing a structure to be aligned on a 64-byte (cache line) or 4096 (page) boundary, in order to, e.g., eliminate false sharing between threads. It's harder to micromanage the memory layout in Go while retaining its safety benefits and native datatypes.
Finally, gcc havs more CPU-specific builtins such as __builtin_prefetch(), which let you have even more control over what data goes into what level of the cache (or doesn't).
I'm interested in compiler development, so this kind of information is really valuable for me... Do you think something similar was achievable in Go, if you had thing like vectors (i.e. fixed-length numerical arrays that would have math-like semantics, and which would compile to SIMD), prefetch attributes/instructions for heap-allocated variables, and memory-alignment attributes for structs or even for specific heap allocations?
gcc can sometimes emit SIMD code for you, without having to think about it. If you need to go farther, it's easy to use something like ispc to write vectorized code and link it into your program. It's more work to take advantage of hyper-optimized C from Go.
Cache-optimized layouts: Not where it comes from, but things like forcing a structure to be aligned on a 64-byte (cache line) or 4096 (page) boundary, in order to, e.g., eliminate false sharing between threads. It's harder to micromanage the memory layout in Go while retaining its safety benefits and native datatypes.
Finally, gcc havs more CPU-specific builtins such as __builtin_prefetch(), which let you have even more control over what data goes into what level of the cache (or doesn't).