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I seriously doubt it's x86 baggage. You don't pay a battery life penalty for code you don't execute.



While you don't use the battery for code you don't execute, when your code is finely tuned to a single machine (as in CPU + auxiliary chips) architecture rather than able to run on a wider choice of hardware, you may be able to squeeze some extra juice from your battery.


Except MacOS X ships fat binaries for multiple CPU architectures and uses a kernel originally designed in the 1980's for an m68k machine.


Shipping fat binaries with different versions for every different Atom/Core/Xeon/FX/Phenom/Opteron Intel/AMD/Nvidia + chipset glue combination would be quite a feat.

This could go well beyond what compiling every package for your specific machine can do.


Openstep supported quad fat binaries iirc, supporting x86, sparc, mips, and I think pa-risc. Gotta say the NeXT software architecture has aged well.


That's not what I was talking about. I said that, if all you support is a specific Intel Atom processor, you can tweak your kernel to support every bit of energy-saving performance-enhancing silicon in there.

Shipping fat binaries is not new. I remember them (not very fondly) from the MacOS 7/PPC days.


True. What is fun is that you could imagine a technology where you would (powering down some unused memory chips), but I don't know if this would be worth it.


Attended a lecture by a grad who implemented this back in 2006. Code resided on the southbridge. Never got commercialized as the penalty of waking/sleeping the chip was not worth the few watts saved. Plus, most servers used all their ram, or near it, all the time.




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