One advantage: the faster the hardware, the more time it can spend in idle states at the same load. So, if you manage to speed up your hardware by a factor X while increasing power usage by a factor < X, it is a net win (I don't know whether they achieve this)
That's not really true for the sorts of architectural changes happening here. Because smaller process nodes mean that leakage power for transistors has grown faster than active power there's now a lot to be said for running those transistors fast for short bursts rather than at a reduced frequency. But adding more transistors still increases your power usage linearly, and performance only goes up with something like the square root of the number of transistors you use. There's things that make this not entirely true on the system level, if a better branch predictor or better cache then you might see less bandwidth to main memory and you'll be saving power there. And you can do things with the silicon level process to reduce leakage power at the cost of performance but then make the performance back up with more transistors and still come out ahead. But in general a smaller core will be more power efficient than a larger one.
