As I understand it, this compiles down to assembly instructions. What then assembles it to machine code? The reason I'm asking is I wanted to find out if the compiler/assembler supports compressed instructions (which are supported by the RP RISC-V core).
Edit: Yes it does support the compressed extension, although the page calls them "compact" instructions.
In the article there is a link to an earlier post with a RISC-V assembler (I think written by the same author), which generates the actual machine code
For me, it's the fact that it is a truly open standard, with no licensing entanglements. It has the potential to be a durable ecosystem, worth investing in.
> Can they really be called registers, when they're bytes in DRAM?
Yes they can, because that's just an implementation detail.
Registers are nothing more than a conveniently short address for frequently-accessed working storage. Sometimes they are in their own address space (which in modern use usually doesn't have indirect/computed addressing, but can), but sometimes they are in the same address space as RAM e.g. in AVR the first 32 bytes of RAM are the registers (which might or might not be implemented in the same technology). Some early / small AVRs didn't have any other RAM. The same is true of PIC and 8051. And then there is the TMS9900 where the only on-chip registers were the PC and a pointer to where in RAM the working registers were stored.
It seems entirely appropriate to refer to the 6502's Zero Page as "registers" given that 1) it barely has any others, and 2) the very fundamental for modern software base+offset addressing mode exists only using two zero page bytes as the base. You would otherwise be reduced to using self-modifying code for any access via pointer.
If the 6502 ISA had not become obsolete for other reasons -- the desire for more than 8 bit ALUs and 16 bit addresses -- it is entirely likely that as CPUs became faster than RAM and more transistors were able to be put in the CPU then future 6502s would have brought Zero Page on-chip.
Going through the system bus IS an implementation detail.
You could build a 6502-compatible CPU with a (extra [1]) 256 byte on-chip register file, and treat, for example, `0x1265` as simply a 16 bit instruction `ADC A,R18`, or `0x0791` as an x86-ish `MOV [R7+Y],A`.
All binary programs would run just as they do on the 1975 6502, just a lot faster.
[1] in the original 6502, the registers aren't in a register file in the modern sense, they're implemented with flip flops and all are accessible simultaneously (with wired-OR on to a bus in some cases if the decode ROM selected several at the same time)
Though no worse than 16 or 32 bit x86 (without FPU), and probably better because the lower 8 registers are general-purpose.
Also you can get something useful from the "spare" five registers r8-r12 as they support MOV, ADD and CMP with any other register, plus BX. Sadly you're on your own with PUSH/POP except for PUSH LR / POP PC.
Thumb-1 (or ARMv6-M) is fairly similar to RISC-V C extension. It's overall a bit more powerful because it has more opcodes available and because RVC dedicates some opcodes to floating point. RVC only lets you do MV and ADD on all 32 (or 16 in RV32) registers, not CMP (not that RISC-V has CMP anyway). Plus, RVC lets you load/store any register into the stack frame. Thumb-1 r8-r14 need to be copied to/from r0-r7 to load or store them.
But on the other hand, RVC is never present without the full-size 4 byte instructions, even on the $0.10 CH32V003, making that a bit more pleasant than the similar price Cortex M0 Puya PY32F002.
My initial experience with Thumb-1 was like stepping on a series of rakes. Can't use ADD? Why not? Oh, it turns out you have to use ADDS. Wait, why am I getting an error when I try to use ADDS? Turns out that inside an ITTE (etc.) block, you can't use ADDS; you have to use ADD. And the various other irregular restrictions on what you can express are similarly unpredictable. Maybe my gripe isn't really with Thumb-1 but with GAS, but even when you learn the restrictions, it still takes extra mental effort to program under them. I did have some similar experiences with 8086 code (it took me a certain amount of trial and error to learn which registers I could use as base registers and index registers, as I recall) but never 80386 code, where all of its registers are just as general-purpose as on Thumb-1, unless you're looking for sizecoding hacks to get your demo down under 64 bytes or whatever.
I agree that RVC is similar in theory, but being able to mix 4-byte instructions into your RVC code largely eliminates the stepping-on-rakes problem, even on Graham Smecher's redoubtable Minimax which Jecel Assumpção mentioned. I still prefer ARM assembly over RISC-V, but both definitely have their merits.
Oh, you're right, of course. I misremembered that rake. I stepped on some others I can't remember now, though.
I wouldn't be surprised to see commercial implementations of Minimax. It seems like it would have a much better cost/benefit ratio than SeRV for some applications.
This is an experimental rather than practical design that only directly implements the compressed instructions in hardware and then implements the normal RV32I instructions in "microcode" written using the compressed instructions.
The LUT counts do look competitive, until you realise that this doesn't include the cost of the microcode.
Probably fine on FPGA where there's lots of almost free BRAM, but on an ASIC where you'd need to use SRAM or mask ROM, or if you used LUTRAM, it would look very different.
Plus, the speed penalty for the microcoded instructions is huge. perhaps not as huge as SeRV :-)
That sounds reasonable, yeah. Presumably you'd write your inner loops purely in RVC instructions; in the situations where you'd use SeRV, you wouldn't be using it for your computational bottlenecks, which you'd build special-purpose hardware for, but just to sort of orchestrate a sequence of steps. But Minimax seems like it could really reduce the amount of stuff you had to design special-purpose hardware for.
I got a RP2350 "Feather"[1] from Adafruit[2]. Amazing little thing, with lots of stuff built-in. The lipoly charge port is super useful and Just Works, and the STEMMA QT connector means no soldering or breadboards for simple projects. My main half-baked idea for this is to control a CPU usage monitor[3], but I also want to make some better lights for my Lego SHIELD Helicarrier, and maybe add some movement too.
And now you're telling me I can use Lisp on this? It would be interesting to see how streamlined the development process is for each one of uLisp, CircuitPython, MicroPython, and Arduino/C.
[3] Yeah I'm rambling but my end goal is to drive an LED matrix that ends up looking like btop's CPU meter. Why not just show btop on a separate small screen? That is a very good question to which I have no answer.
I don't think it's yet complete enough to compile itself; though I haven't looked at the assembler code, I'm pretty sure it requires bitwise operations the compiler can't compile yet. Also, the compiler itself requires things like null, symbolp, eq, and atom, which it also doesn't implement yet. Without those I'm not sure that it's fair to describe its input language as Lisp, though it does support car and cdr.
But it's still super cool. A really great thing about Lisp for purposes like this is that you don't get hung up on syntax and parsing, which is the most salient part of writing a compiler but not the most important.
Things like atom and symbols are functions in the runtime. A Lisp compiler only has to handle special forms, and function calls. If we see the compiler source code using a special operator that it doesn't handle, either directly using it or via macro expansion, then we know it's not yet self-hosting.
Handling specific functions is optional. If the compiler can compile a function call, it can compile a call to the + or car functions, which then have to be president in the run-time.
Functions like these are obvious targets for special recognition and inlining. Arithmetic code won't be as fast as it could be if every + has to be a call to a function, but it will work.
A compiled Lisp implementation can be bootstrapped to the point where the definition of car in the library looks like:
(defun car (x) (car x))
And similarly for some other functions. Then there are only two places in the system that know how to actually extract the car field: the compiler source code, and the corresponding compiler executable needed for bootstrapping.
In that case if you remove the car handling from the compiler then the system's self-hosting and bootstrapping ability breaks.
Of course! That's what I did last time I wrote a Lisp compiler, but this one seems a little more limited. The page explains:
> Finally, comp-funcall compiles code for function calls to the built-in functions, or a recursive call to the main function: (...)
(Emphasis mine.)
And none of his example functions calls any function other than the builtin ones (which, indeed, his compiler does inline) and itself. But it isn't obvious where the limitation comes from; the subroutine call is just a jal instruction to an assembler label, which you would think would work just as well to call another function as to make a recursive call.
Maybe the limitation is that the assembler only assembles a single function at a time, and he doesn't have a link-editing stage or a symbol table implicitly or explicitly shared between assembler calls. In that case it would be fairly simple to extend the compiler to support more general calls, as you reasonably but apparently incorrectly assumed this one already does.
Looking a bit at the assembler http://www.ulisp.com/list?31OE it looks like it only supports jumps to previously defined labels? In $jal and offset I don't see anything that resembles adding a relocation to a list of relocations for a label so it can be backpatched later. But I also don't see how it gets the numerical value for a label that it subtracts *pc* from in offset. In the compiler itself http://www.ulisp.com/list?4Y4Q it seems to be consing up lists of assembly instructions that eventually get evaled, which seems like a kind of janky way to invoke your assembler but whatever, but I don't see where the binding of label names to addresses happens. I can't find anything resembling a symbol table.
I think I'd make a few other changes, though. I'd add closure support and some kind of type tagging; right now it depends on knowing the types are compile time so it's kind of more like a Forth or C compiler with Lisp syntax. And I'd indirect the calls through a runtime-mutable symbol table so you could redefine a function without having to rewrite all the calls to the old function in existing code.
That's what I did last time I wrote a Lisp compiler, anyway; maybe it's not a good tradeoff on today's hardware anymore, since people presumably still only interactively load new definitions a few times a minute at most, but CPUs have gone from a MIPS to a hundred BIPS. So making all your function calls much slower by frustrating the CPU's branch predictor with a PLT in order to speed up relinking after an edit might no longer be a good tradeoff, even if it is what glibc does—glibc doesn't have FASLs.
The assembler is two-pass and the labels are simply local variables in the defcode form. They are assigned the value of the program counter in the first pass, and the assembler instructions are evaluated in the second pass. I got the idea from the assembler in the Acorn Atom, if anyone remembers that.
> So I think the compiler may not be able to compile calls to arbitrary functions?
A Lisp compiler will by default compile a call to ANY function as a "jump subroutine" (or as a non-returning jump in the case of a tail call) machine code call. The function then has to be present at runtime (in the runtime) and the code will call it at runtime. Lisp code by default also calls a global function through its symbol's cell -> late binding.
"supported by the compiler" here probably means that the compiler can generate inline code for these functions in various cases. Thus if the call is to the function 1+ and it knows that the argument is an integer number (and, possibly, the result also has to be an integer number), then it will not use a subroutine call via the global function, but will inline the call to an integer addition machine instruction. Obviously this then defeats late binding.
If a Lisp (for a tiny machine) only has fixnum integers as its single numeric data type, then the thing is simple -> every 1+ will get an integer argument and thus one can inline it. Inlining makes for tiny computers (which uLisp was developed for) only sense if the inlined function code isn't too long and doesn't use to much of the precious memory for the machine code. Inlining OTOH like will have a positive effect in reducing execution time and a negative effect by increasing compilation time.
In languages like Common Lisp or Scheme, which have several numeric types (fixnums, bignums, floats, ratios, complex, ...) this gets more complicated. Common Lisp compilers typically use optional type declarations and type inference to determine what inlined code to generate.
This is all very neat and all but could anyone please explain to me how this thing handles forward label resolution e.g. in the "if" construct? I think I know how it does that but I am very likely to be be wrong.
I was going to say nothing in the RISC-V world is comparable to the N100 yet, at any price, but it looks like the N100 is anywhere from 10 to 20 times faster than the N270.
Geekbench 6 doesn't have any N270 results but it has a couple of Atom 230 results, and other sources indicate those two are very similar.
So, ok, on Geekbench a single core of the JH7110 comes in a bit faster than the Atom 230. And it's got four of them. You can get a Milk-V Mars CM with a 1.5 GHz JH7110 with 2 GB RAM for $34. You should be able to build a decent little netbook around that for $100. It's compatible with the Raspberry Pi 4 CM, so if there is a suitable netbook enclosure for the Pi 4 CM then it should work.
Otherwise I think the ClockworkPi DevTerm R-01 would be the closest that actually exist at the moment. The single 1.0 GHz C906 core is a bit slower and the price is unfortunately $239.
You can always reduce the number of jobs from make/ninja to 4...
But, yes, you are right; the issue lies on linking. LibTD requires 2GB as minimum, but linking takes ages. At least with GCC, Clang requires far less RAM.
