> I honestly think the very readable specification has been a boon for RISC-V and possibly part of the reason why people continue to find it easy to pick up.
Totally agree
> If you are unsure about something in the spec, there's also a multitude of RISC-V emulators out there, probably several in your favorite language already.
...but this is a problem. This means that it's not the specification saying what the standard is, but an implementation. People copying different implementations get different behaviours.
Am I the only one that thinks an implementation is actually the better specification, if readable? What better way to describe state mutations than actual code, provided the language used is well-specified?
Readability is key here, as the opposite, a black box emulator, would not provide the same value.
> People copying different implementations get different behaviours
People copying black box behavior get different behaviors, necessarily.
Using English results in palpability, not specification. Major distinction. Indeed specs are intended to make an hitherto unseen vision palpable. But it's better to provide a mold, and verify implementations fit the mold.
Totally agree
> If you are unsure about something in the spec, there's also a multitude of RISC-V emulators out there, probably several in your favorite language already.
...but this is a problem. This means that it's not the specification saying what the standard is, but an implementation. People copying different implementations get different behaviours.