That's because in NMOS logic (maybe there's a symmetric reason in TTL, but I don't know for sure) you can implement a NOR with two parallel transistors between a pullup and ground, producing a zero output if either input is high. The symmetric NAND circuit requires two transistors in series, and therefore switches more slowly.
Conversely, PMOS logic has the exact opposite problem - NAND gates are parallel, while NOR gate are series.
Meanwhile, CMOS logic inherits both of these problems (in return for better performance in general), but due to semiconductor chemistry, PMOS transistors are weaker than NMOS ones (which was why NMOS was more widely used than PMOS in the first place), so NAND gates have two strong transistors in series and two weak transistors in parallel, which gives a better worst-case switching speed than a NOR gate (where the weak transistors are in series, and so switch noticably slower). This is where "NANDs are used for everything" comes from.
