On: JEDEC Extends DDR5 Memory Spec to 8800 MT/S, Adds ...

[foota]

Most of the cost of an L3 miss comes after the miss itself, for most architectures I've seen.

E.g., on Skylake an L3 hit is 80 cycles (~20ns) whereas a RAM access is 80 cycles plus 50 nanos (~70 nanos). See https://www.7-cpu.com/cpu/Skylake_X.html

[luyu_wu → foota]

From my rough knowledge of textbooks RAM access is usually in the hundreds of cycles. The napkin math makes more sense in that order of magnitude too! In any case it seems unlikely L3 has similar latency considering memory heirachy!

Interesting discussion though!