Not directly, but I think it could be an alternative to the carry flag present on most CPU architectures (today that means x86 and ARM, and also historically pretty much anything else that was at all significant).
The much-hyped RISC-V is one of the few that doesn't have a flag register, because it's been claimed to be a performance bottleneck - in my somewhat heretical opinion, the actual reason is that its designers are deluded into thinking that C and UNIX are as fundamental to software as transistors are to hardware, and thus anything beyond what's needed to support that environment is not worth implementing.
But an extra bit per register would be like having a separate carry flag for each, potentially solving some problems with parallelization and also allowing checks for integer overflow at the point a value is stored into memory or used in a subsequent operation.
Having some kind of carry flag enables various programming tricks that can also be useful for SWAR, for example subtract-with-carry of a register with itself will either set or clear all bits.
I had a question recently: would an extra 65th bit in some registers have a good use case with stuff with SWAR?