Each fab is the development of an entire "process". Furthermore how the machines are used varies greatly. Everything from exact doping and cleaning processes to metal deposition parameters, plus the masks you feed into the system which these days are all interference-based - that is you rely on the interference patterns because you can't actually make masks nor use light of a wavelength small enough to create 14/10/7nm feature sizes. The mask you make is nonsense but the interference pattern it creates results in the actual patterns you want.
How many layers, how you can intersperse metal vs silicon layers, allowed dimensions for gates, wires, distances between components, and a whole host of other things are unique to the specific process. Oh and parameters vary based on what you are making on a given process (eg SRAM vs logic). Different layers can have different requirements as well. You might not even be able to take a design to another fab from the same company on the "same" process node, let alone a competitor.
This stuff is all extremely closely guarded by every fab. If you're a serious customer (read: $$$$) the fab will share these parameters with you so your engineers can design to that spec. Then your first run will likely have problems and need to work with the fab engineers to tweak layouts and such to get usable yields - depends on how much you are relying on the fab for design/layout. TSMC will happily license you certain blocks to use in your design along with guarantees on yield since the design is made for their process from the start. You can also license designs (eg from ARM) that are pre-customized for a given fab's process.
Each fab is the development of an entire "process". Furthermore how the machines are used varies greatly. Everything from exact doping and cleaning processes to metal deposition parameters, plus the masks you feed into the system which these days are all interference-based - that is you rely on the interference patterns because you can't actually make masks nor use light of a wavelength small enough to create 14/10/7nm feature sizes. The mask you make is nonsense but the interference pattern it creates results in the actual patterns you want.
How many layers, how you can intersperse metal vs silicon layers, allowed dimensions for gates, wires, distances between components, and a whole host of other things are unique to the specific process. Oh and parameters vary based on what you are making on a given process (eg SRAM vs logic). Different layers can have different requirements as well. You might not even be able to take a design to another fab from the same company on the "same" process node, let alone a competitor.
This stuff is all extremely closely guarded by every fab. If you're a serious customer (read: $$$$) the fab will share these parameters with you so your engineers can design to that spec. Then your first run will likely have problems and need to work with the fab engineers to tweak layouts and such to get usable yields - depends on how much you are relying on the fab for design/layout. TSMC will happily license you certain blocks to use in your design along with guarantees on yield since the design is made for their process from the start. You can also license designs (eg from ARM) that are pre-customized for a given fab's process.