I'm not sure if the idea[1,2] is stupid, or brilliant... and I'm not arrogant enough to assume its brilliant. I've been nerd sniped by it though, since the 1980s.
The basics are simple enough, imagine an FPGA without any routing hardware, just a sea of 4 bit in, 4 bit out Look Up Tables (LUTs). To prevent race conditions, I'd latch the outputs of the cells, and clock then in 2 alternative phases.
This makes the thing a horrible FPGA, because latency is the one thing they fight hard to overcome, but on the other hand, it makes it very easy to reason about, and immune to race conditions, timing issues, etc. The gain is that you get almost trivial routing, and essentially all of the transistors devoted to compute.
It's what you get when you answer George Gilder's call to "waste transistors".[3]
I've got a simulator for the chip, I still need to figure out how to program it (i.e. write a compiler, debugger, etc.)
The major question.... can this architecture do an Exaflop on a cheap chip? (<$10 in quantity)
The basics are simple enough, imagine an FPGA without any routing hardware, just a sea of 4 bit in, 4 bit out Look Up Tables (LUTs). To prevent race conditions, I'd latch the outputs of the cells, and clock then in 2 alternative phases.
This makes the thing a horrible FPGA, because latency is the one thing they fight hard to overcome, but on the other hand, it makes it very easy to reason about, and immune to race conditions, timing issues, etc. The gain is that you get almost trivial routing, and essentially all of the transistors devoted to compute.
It's what you get when you answer George Gilder's call to "waste transistors".[3]
I've got a simulator for the chip, I still need to figure out how to program it (i.e. write a compiler, debugger, etc.)
The major question.... can this architecture do an Exaflop on a cheap chip? (<$10 in quantity)
[1] https://esolangs.org/wiki/Bitgrid
[2] https://github.com/mikewarot/Bitgrid
[3] https://www.wired.com/1993/04/gilder-4/