On: UltraRAM

[agumonkey]

Noob question, aren't the trillions of cycle including 'refreshing' read/write that wouldn't be necessary with persistent memory ?

[adrian_b → agumonkey]

You can trivially exceed one million write cycles in only a second with a modern CPU, just by incrementing a shared counter (which cannot be cached).

[adwn → adrian_b]

> just by incrementing a shared counter (which cannot be cached)

That's not true, a shared counter (i.e., an atomic integer) is cached – in fact, there's no guarantee that its value is ever written back to system RAM.

You're probably thinking of non-cacheable memory: the kernel can set the MMU attributes of a memory page such that the CPU will avoid the cache when it accesses addresses in that page. This is completely independent of atomic accesses on memory locations [1].

[1] At least typically – there may well be CPUs which disallow atomic accesses on non-cacheable memory.

[SonOfLilit → adwn]

I assume by "which cannot be cached" he meant "which is in a page configured as non-cacheable in the MMU", i.e. exactly what you said

[adwn → SonOfLilit]

But then why would it have to be a shared counter? Any write to a non-cacheable memory location is transmitted to system RAM, it doesn't have to be shared with other cores, nor does it have to be a counter.

[tuatoru → adwn]

Because it is used by a peripheral.