the question of pynq support is addressed/implicated in several places (timing/delay maps, tech mapping, bitstream generation).
the short of it: this shit is proprietary/encumbered beyond belief.
the medium of it: there are OSS flows that can generate bitstreams for pynqs (depending on the actual FPGA part) but they are not at all supported by AMD (formerly Xilinx) and rely on rev-eng work. the problem is while burning a bitstream is important, it's not the only thing you need to make OSS worthwhile. in particular you need the timing/delay maps and as far as i know, those are all shipped encrypted with vivado (and the cracks haven't been released).
https://docs.verilogtorouting.org/en/latest/vtr/cad_flow/#vt...
the question of pynq support is addressed/implicated in several places (timing/delay maps, tech mapping, bitstream generation).
the short of it: this shit is proprietary/encumbered beyond belief.
the medium of it: there are OSS flows that can generate bitstreams for pynqs (depending on the actual FPGA part) but they are not at all supported by AMD (formerly Xilinx) and rely on rev-eng work. the problem is while burning a bitstream is important, it's not the only thing you need to make OSS worthwhile. in particular you need the timing/delay maps and as far as i know, those are all shipped encrypted with vivado (and the cracks haven't been released).