>Can't even load a 32-bit constant into register with a single instruction on RV.
Just do it in the standard way, and not concern yourself with hardware implementation details. RISC-V assembly language even has standardized pseudoinstructions to do just that.
Some implementations will see the multiple opcodes as one instructions. Others won't. It's not for the programmer to worry about.
The standard does not actually specify what sequence of instructions to use for the load pseudo-instruction, so it is left up to the assembler to decide.
A 32-bit load still requires 2 instructions (The purpose of the lui instruction is to make this efficient). A 64-bit load requires loading 2 32-bit values, shifting one 32-bits right then performing a bitwise or. Alternatively you can hold the 64-bit value in .rodata and use a single instruction to load it.
The point is, it takes several more instruction bits and/or cycles than a `shr 2; sar 2` for clearing the two MSBs, so the optimisation given for x86 for this sequence is not useful here and the trivial solution is better.
A solution that may be better elsewhere is `btr 63; btr 62`. Since RV can specify a different destination operand you don't need an extra mov instruction as the x86 version would require.
Just do it in the standard way, and not concern yourself with hardware implementation details. RISC-V assembly language even has standardized pseudoinstructions to do just that.
Some implementations will see the multiple opcodes as one instructions. Others won't. It's not for the programmer to worry about.