You'd probably want to add at least a small cache, sure. Putting the zero page (256 bytes) on-die on each core (because it's typically used as "extra registers" of sort in 6502 code) plus a small additional instruction cache could do wonders. But you probably still wouldn't get anywhere near enough performance for it to be competitive with a more complex modern architecture.
It'd be a fun experiment to see someone do in an FPGA, though.
It'd be a fun experiment to see someone do in an FPGA, though.