> Can someone who knows better than me please comment on the Linux server scheduling issues with a CPU like this.
The scheduler was more or less designed around symmetric multi processing. BIG/little asymmetric systems will still have obviously preferred cores; if you're optimizing for throughput, add one task to each fast core first, then to each slow core, then maybe move tasks around to fit policies, etc.
With the 7900X3D and the 7950X3D, it's trickier, because one chiplet has a lower clock speed but more cache. Tasks that fit into the smaller cache will do better on the less cache chiplet, and tasks that fit into the larger cache but not the smaller cache will do better on the larger cache chiplet, and tasks that don't fit into either task will probably do better on the faster chiplet, but it kind of depends. In order to make good decisions, the scheduler would need more information about the task's memory access patterns, and I don't think that's something schedulers tend to keep track of; but if this type of chip is common in the future, it will need to happen.
For Epyc, AMD's server processor line, I believe the plan for X3D is to add cache to all the chiplets, keeping them roughly symmetric; there's still the modern situation that some cores will boost higher than others, and moving tasks to different cores can be very expensive if the process has memory still resident in cache on the old core, and the new core doesn't share that cache, etc.
The scheduler was more or less designed around symmetric multi processing. BIG/little asymmetric systems will still have obviously preferred cores; if you're optimizing for throughput, add one task to each fast core first, then to each slow core, then maybe move tasks around to fit policies, etc.
With the 7900X3D and the 7950X3D, it's trickier, because one chiplet has a lower clock speed but more cache. Tasks that fit into the smaller cache will do better on the less cache chiplet, and tasks that fit into the larger cache but not the smaller cache will do better on the larger cache chiplet, and tasks that don't fit into either task will probably do better on the faster chiplet, but it kind of depends. In order to make good decisions, the scheduler would need more information about the task's memory access patterns, and I don't think that's something schedulers tend to keep track of; but if this type of chip is common in the future, it will need to happen.
For Epyc, AMD's server processor line, I believe the plan for X3D is to add cache to all the chiplets, keeping them roughly symmetric; there's still the modern situation that some cores will boost higher than others, and moving tasks to different cores can be very expensive if the process has memory still resident in cache on the old core, and the new core doesn't share that cache, etc.