This platform exposes each CCX ( group of 4 cores which share the L3 between them) as a NUMA domain if you want. This means that if your workload really takes a huge performance penalty from the ~10% lower (still very high) clock speed, or only part of it really enjoys the cache, you can manually tell the OS to stay where you want.
Scheduling for this kind of chip is not super, but it might improve. Meanwhile, you can enjoy almost all of the performance for the specific workloads where it matters by doing this.
Scheduling for this kind of chip is not super, but it might improve. Meanwhile, you can enjoy almost all of the performance for the specific workloads where it matters by doing this.