As that article points out, CPUs consist of both logic and RAM. Even in a worst case scenario where RAM doesn't scale down you still get a huge performance and/or efficiency boost.
To quote:
> Of course, the impact won’t be felt the same across the board. The percentage of SRAM and caches on chips varies greatly by your target market and overall capabilities
and
> Beyond SRAM, the industry has been looking into many other alternative memory architectures. Emerging memory technologies include MRAM, FeRAM, NRAM, RRAM, STT-RAM, PCM, and others. Those emerging memory bitcells offer unique tradeoffs when compared to SRAM such as higher density at lower read/write specifications, non-volatility capabilities, lower read-write cycle capabilities, or lower power at potentially lower density or speeds. While they are not direct replacements for SRAM, moving forward they might play a role as level 4 or level 5 caches where the lower performance tradeoffs can be offset by higher density.
Isn't this problem solved with a chiplet design like AMD does? Just manufacture the SRAM using an older and cheaper node and keep the logic in the most advanced node.
And? Just because one aspect isn’t scaling well doesn’t mean the rest being scaled is pointless.
Besides the fact they will probably figure out a way to either replace sram with something else that does scale better or they will figure out novel techniques to scale sram.
To quote Newt from alien 2, "Ripley, it won't make a difference!" because SRAM is NOT scaling down!
https://fuse.wikichip.org/news/7343/iedm-2022-did-we-just-wi...