Interesting. Why with SRAM is switching so much more power consuming than just maintaining? I thought with a flip flop every gate is used on pretty much every cycle while it feeds back on itself.
I would have thought reading/writing SRAM is much more expensive than idling it not because of the cost of toggling the flip-flop, but all the cache coherency stuff associated with making a change in multicore.
I would have thought reading/writing SRAM is much more expensive than idling it not because of the cost of toggling the flip-flop, but all the cache coherency stuff associated with making a change in multicore.