CPU of the Day: UTMC UT69R000: The RISC with a Trick (2019)

[zdw]

https://www.cpushack.com/2019/03/01/cpu-of-the-day-utmc-ut69r000-the-risc-with-a-trick/

[snvzz]

Reminder that RISC/CISC are labels placed upon an ISA (the software-hardware interface).

The microarchitecture (how the CPU is internally designed, how it executes instructions) is irrelevant to RISC vs CISC.

[steponlego → snvzz]

This might be mostly true now but wasn't always.

[somat]

If curious as to what a 1750 architecture cpu is. there is this.

http://www.xgc-tek.com/manuals/mil-std-1750a/

[formerly_proven → somat]

> Copyright © 1980, 1982 by USAF

Isn't that an oxymoron?

[somat → formerly_proven]

True, My understanding is works created by the federal government are for the public good and are as such in the public domain. Note that they can still limit distribution. mainly this is done via classifying the work. Also note the public domain may not apply to works created for the federal government by a third party. final note. The good state governments follow the federal government in placing things in the public domain, but some states try to copyright works they have made. Boo hiss.

[drivers99]

> The UT69R000 [has] a 64K data space and a 1M address space.

So the virtual address space is 1M but it can only physically interface with 64K of memory?

[hummus_bae → drivers99]

The chip itself can have up to 64k Flash (and another 64k of RAM). But the CPU accesses the memory via a MMU that can map the 1M address space into (mostly) 64k chunks. So effectively the OS can use 1M physical addresses and the CPU itself uses close to 64k of them (depending on how you configure the MMU).

edit: so the whole address space of 1M can be mapped via the MMU into 64k installments.

[AnotherGoodName → hummus_bae]

Pretty similar to many CPUs of that era. x86 included.

https://en.wikipedia.org/wiki/X86_memory_segmentation

[postalrat → AnotherGoodName]

And the many mappers NES and other consoles used: https://www.nesdev.org/wiki/Mapper