There is a limit, but it depends on the materials and transistor geometry because those shape the potential wells, which affect tunelling. For example, high-κ dielectric materials. From Wikipedia:
> As the thickness [of the gate insulator] scales below 2 nm, leakage currents due to tunneling increase drastically, leading to high power consumption and reduced device reliability. Replacing the silicon dioxide gate dielectric with a high-κ material allows increased gate capacitance without the associated leakage effects.
In other words, the limit hasn't been reached yet.
Also bear in mind 3nm is a marketing number which has a tenuous connection to a technical feature of the lithography. These days it's really just a number which shrinks with each generation to indicate which generation. The transistors are not actually 3×3 nm in size; they are larger.
