>TSMC and Samsung have adapted to new generations without any real hiccups
Samsung has been having serious issues for years and TSMC is currently having serious issues with N3. Samsung's issues are too complicated and longstanding to go into but TSMC's issues are simpler and more recent. Their base N3 process (now called N3B) is a bit of a dud with apple being essentially the only major customer. The issue is with cost and yields, N3B just doesn't make economic sense for most customers. TSMC is aware of this and is racing to fix this. The fix is known as N3E which is an "enhanced" "version" of N3. The reason I put quotes around both of those words is because N3E actually has relatively little to do with N3B, there is no direct path to transition N3B chip designs to N3E, and because it features some improvements, but also some significant regressions in performance compared to N3B. The highest profile regression is the total lack of SRAM density improvements compared to N5. Sticking a huge chunk of SRAM on the chip has become very important to modern chip performance so this is a really big deal. The process is "enhanced" mostly in terms of economics, not performance, and it's coming an entire year after N3B. This has essentially delayed TSMC's "real" N3 node an entire year while also reducing its performance advantage over competitors. There's been a lot of discussions about the implications of this in the hardware space[1][2]
Samsung has been having serious issues for years and TSMC is currently having serious issues with N3. Samsung's issues are too complicated and longstanding to go into but TSMC's issues are simpler and more recent. Their base N3 process (now called N3B) is a bit of a dud with apple being essentially the only major customer. The issue is with cost and yields, N3B just doesn't make economic sense for most customers. TSMC is aware of this and is racing to fix this. The fix is known as N3E which is an "enhanced" "version" of N3. The reason I put quotes around both of those words is because N3E actually has relatively little to do with N3B, there is no direct path to transition N3B chip designs to N3E, and because it features some improvements, but also some significant regressions in performance compared to N3B. The highest profile regression is the total lack of SRAM density improvements compared to N5. Sticking a huge chunk of SRAM on the chip has become very important to modern chip performance so this is a really big deal. The process is "enhanced" mostly in terms of economics, not performance, and it's coming an entire year after N3B. This has essentially delayed TSMC's "real" N3 node an entire year while also reducing its performance advantage over competitors. There's been a lot of discussions about the implications of this in the hardware space[1][2]
[1]https://www.semianalysis.com/p/tsmcs-3nm-conundrum-does-it-e...
[2]https://fuse.wikichip.org/news/7048/n3e-replaces-n3-comes-in...