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I'm coming from a side where people are nowadays literally working with their own FPGAs to get more performance though haha



Hopefully they are doing VHDL with formal verification, for the sake of their data consistency.


I'm currently working with very good researchers on formal verification of a part of the software I'm writing in rewriting logic with Maude - formalizing a fairly simplified version of the execution engine algorithms (0.005% of the c++ codebase maybe, 2500 lines of c++ at most) is taking ~a year roughly so far. That's not really viable for general development especially with requirements which evolve all the time.




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