It's interesting to note the smaller TPA size on the Master (25kB) vs C64 (46kB) as the Master came with 128K minimum.
I know that the Master still had a 16bit address bus but I was under the impression that it would still be possible to get access to a full 64K in one go if needed (the rest being paged in and out).
No, the Master followed the BBC Micro architecture, which was 32K RAM followed by 32K ROM, made up of 16K paged ROM then 16K of OS and memory mapped peripherals. The other 96K that made up the 128 was 64K in sideways RAM (which could be paged into the pages ROM area, 20K that could be paged over the top of the RAM (where the screen data would live) and 12K that could be paged over parts of the OS ROM.
On the Master I could fairly easily extend the TPA up into the sideways RAM area, adding another 16kB, for a total of probably about 45kB. The difficulty is that filesystems in Acorn's MOS can't access sideways RAM directly, as that's where the filesystem module itself lives, so all I/O would have to be done by copying the data to low memory, calling MOS, then switching the sideways RAM back in again afterwards. There may also be subtleties in catching interrupts and things which might try to change sideways RAM pages. But it should totally work.
For the _really_ advanced version, it could run bare metal and reuse the OS workspace at 0xc000 all the way up to 0xe000. But that would lost all MOS services, so would have to reimplement things like screen redrawing and floppy disk handling.
I know that the Master still had a 16bit address bus but I was under the impression that it would still be possible to get access to a full 64K in one go if needed (the rest being paged in and out).