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> Because of that, 64-bit architectures use only 48 lowest bits of every pointer which still give plenty of addresses. It means that only 48 bits in a pointer are significant and that is enough for our NaN boxing.

Congratulations, you have just ruined your software's forward c11y.

Those 16 bits aren't going to stay reserved forever.




48 bits lets you have 256 terabytes of addressable memory. If you go to 56 bits, you get ~64 petabytes of addressable memory. 48 bits is probably good for 5-10 years as we hit the limits of process shrinks. 56 bits should be good for a quite a bit longer. This is all assuming we don't find some magical memory tech that lets us add orders of magnitude more memory without needing absurd amounts of cooling and power.


I don’t understand what you mean. In your process, you can control the address range of your memory, so the address range of your pointers. It’s irrelevant if the 16 bits are reserved by the architecture or not - just don’t map space that uses them. What’s the issue?


In fact, today already there are CPUs that support larger address spaces. But OSes should be smart and only provide pointers with the top 16 bits free while the application fits - even if some programs in the future end up using >256TB of address space, not all will, and those that don't should be able to take advantage of 48-bit pointers.

Moreover, a single program could even take advantage of a "low heap" that stores metadata, and can have 48-bit pointers pointing to it, and a "high heap" of the actual large data (whose addresses take the full 64 bits, but may include tagged pointers to the low heap without doubling the memory footprint of the already humongous 256TB)


When? Too long to care.

How long will it be until 256TB of RAM (which is what 48 bits will address) becomes even remotely common in a single system? Even 256GB, 1024x less, is not common today, except in huge servers.

How long will it take to change the implementation when/if it does?

I've seen far too much "future proofing" that makes the present worse, for a future that might never even happen.


Quad-precision floats will be widespread before applications that use >256TiB of memory are common.

In that case, we can NaN-box the quad float and have up to 112 bits of pointer space to play with. Lets assume we double the number of pointer bits to 96 - we can support YiBs of address space.




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