RISC-V does not in any way depend on instruction fusion. I don't why this meme persists, especially as no RISC-V cores in the market do instruction fusion.
High end OoO cores in other ISAs are BREAKING DOWN complex instructions into µops. RISC-V is pre-broken down. The one exception to that is current x86 and ARM cores DO do instruction fusion, to combine a compare with a following conditional branch. Which is a singe instruction in RISC-V in the first place. SO it is actually the other way around.
Low end cores shouldn't be doing either fusion or breaking down into µops. They are supposed to be as simple as possible, and doing either of those is a complication using significant silicon area and energy.
There might be a place for instruction fusion in mid-range cores. Things in the ARM Cortex A53 / A55 / A510 range. The most popular RISC-V core in that segment, the SiFive U74 (used in the HiFive Unmatched, BeagleV Starlight, VisionFive v1, VisionFive 2, Pine64 Star64 .. and probably more yet to be announced) doesn't fuse multiple instructions into one instruction, but it does pair a forward conditional branch past a single instruction with that following instruction. Both instructions still exist, they each go down one of the two execution pipelines side by side, the same as if the branch was predicted not-taken. At the final pipe stage if the branch turns out to be taken, instead of taking a mis-predicted branch penalty and flushing the pipeline, the U74 simply does not write the result of that following instruction back to the destination register.
That's the closest any currently shipping RISC-V core I know of comes to instruction fusion.
"crazy difficult to implement levels of instruction fusion" does not exist anywhere, and is not needed. It's just an idea from an academic which doesn't actually exist in the real world, at least at present.
The meme persists because the ISA has a lot of “simple” instructions that don’t actually match what real world software would like to make performant, so a bunch of RISC-V enthusiasts handwave it away as “oh the chip will just fuse all the instructions and make it efficient”.
High end OoO cores in other ISAs are BREAKING DOWN complex instructions into µops. RISC-V is pre-broken down. The one exception to that is current x86 and ARM cores DO do instruction fusion, to combine a compare with a following conditional branch. Which is a singe instruction in RISC-V in the first place. SO it is actually the other way around.
Low end cores shouldn't be doing either fusion or breaking down into µops. They are supposed to be as simple as possible, and doing either of those is a complication using significant silicon area and energy.
There might be a place for instruction fusion in mid-range cores. Things in the ARM Cortex A53 / A55 / A510 range. The most popular RISC-V core in that segment, the SiFive U74 (used in the HiFive Unmatched, BeagleV Starlight, VisionFive v1, VisionFive 2, Pine64 Star64 .. and probably more yet to be announced) doesn't fuse multiple instructions into one instruction, but it does pair a forward conditional branch past a single instruction with that following instruction. Both instructions still exist, they each go down one of the two execution pipelines side by side, the same as if the branch was predicted not-taken. At the final pipe stage if the branch turns out to be taken, instead of taking a mis-predicted branch penalty and flushing the pipeline, the U74 simply does not write the result of that following instruction back to the destination register.
That's the closest any currently shipping RISC-V core I know of comes to instruction fusion.
"crazy difficult to implement levels of instruction fusion" does not exist anywhere, and is not needed. It's just an idea from an academic which doesn't actually exist in the real world, at least at present.