RISC-V is very flexible, yes, but most 'desktop-class'/application processors are expected to implement at least RV64GC. G is short for IMAFD, so mul/div, atomics, and floating point are all in there, as well as compressed instructions (C) to reduce code size.
Other features you're likely to want are also included in the specification, so if you want to write code that uses for example the B bit manipulation extension or the V vector extension (which is scalable with vector width as well, unlike SSE/AVX) you just have to check a standardized 'CPUID' bit and can run your code, and otherwise fall back to other code.
I also believe that the spec may let operating systems hook these instructions and provide fallbacks so application developers don't have to, but I'm not too sure on the specifics of the privileged ISA of RISC-V.
Other features you're likely to want are also included in the specification, so if you want to write code that uses for example the B bit manipulation extension or the V vector extension (which is scalable with vector width as well, unlike SSE/AVX) you just have to check a standardized 'CPUID' bit and can run your code, and otherwise fall back to other code.
I also believe that the spec may let operating systems hook these instructions and provide fallbacks so application developers don't have to, but I'm not too sure on the specifics of the privileged ISA of RISC-V.