Back then the big EDA outfits were Mentor Graphics, Daisy, and Valid. ECAD became Cadence, embraced silicon compilers, and ate everybody's lunch.
Back then, chips were still laid out by pasting up prepared logic blocks, gates, and occasional custom transistors, and routing metal traces between them, all on what we would today call a low-resolution workstation monitor. A million transistors was a lot. These would be output via a plotter to make photomasks for the various doping, glass, and and metal layers.
The EDA software of the time, besides supporting manual editing editing of layouts and schematics, would simulate whole chips taking into account capacitance of wires and transistor inputs, propagation delay, and drive capability of output transistors. It would also apply geometric checks to make sure the layout conformed to rules of the target process. Where violated, somebody would need to redraw that bit, which might mean moving stuff out of the way.
Somebody would have to make up sequences of values to feed to inputs, and others to check outputs against.
So the period when MG was buying and shuttering silicon compiler startups was '85 to '89.
I think after Cadence won, Mentor Graphics got more involved in supporting embedded system design and firmware integration, leaving chips to others. Daisy merged with Cadnetix and went bust in 1990, and after twists and turns what was left became part of Mentor Graphics in 1999. Valid was folded into Cadence in 1991.
Cadence tried and failed to buy MG in 2008. MG was finally bought by Siemens AG in 2016.
Silicon compilation takes place in three major steps:
Convert a hardware-description language such as Verilog or VHDL into logic (typically in the form of a "netlist").
Place equivalent logic gates on the IC. Silicon compilers typically use standard-cell libraries so that they do not have to worry about the actual integrated-circuit layout and can focus on the placement.
Routing the standard cells together to form the desired logic.
So this is basically what I do everyday but we just call it logic synthesis (Synopsys Design Compiler / Cadence Genus) and Place and Route in Cadence Innovus or Synopsys IC Compiler. We use Mentor Calibre for LVS/DRC.
I've worked in serdes teams where there is a lot of custom analog design with manually sized transistors and custom layout in Virtuoso. I'm working on chips in 5nm that are over 20x20mm so it would be impossible to do those without all the automation and it is still tons of manual work.
Some of my older coworkers told me about doing layout on transparencies and colored pencils in the early 1980's.
I have been out of that world for 30 years. The terminology has stabilized since, and the software has got overwhelmingly more sophisticated, and also (I hear) comically buggy. Comically if you are not obliged to rely on it. Maybe tragically, otherwise, with no expectation of improvement.
Some of us remember Rubylith with conflicted fondness.
I design semiconductors and I use EDA software everyday.
I know Cadence was formed from a merger in 1988 and they have since bought around 30 other EDA companies.
https://en.wikipedia.org/wiki/Cadence_Design_Systems