Strangely the language "below" assembly, Verilog, is a lot more abstract and tries to pretend to look like C while generating hardware, so writing it is more like imagining how to trick it into doing what you want.
That's because a HDL is not a lower level machine language, but instead they are languages used to implement a machine that consumes a machine language.
Consider what happens when you implement a x86 emulator in python: you're using a high level language to implement a machine using a particular substrate (a simulation inside another machine). This simulated x86 CPU executed machine code and you'd call that machine code to be the "native" or "lowest level" language with respect to that particular machine.
You can see how that choice of machine language bears no relationship with the language used to implement the underlying machine.
