On: How fast can a 6502 transfer memory?

[rasz]

https://en.wikipedia.org/wiki/CSG_65CE02#Pipeline_improvemen... fixed most painful ones, but afaik not all dead cycles. But it was 1988 and commodore didnt bother putting it into anything other than some IO card for the AMIGA, not to mention it still did nothing to cover slowness of moving data around. Japanese decided to do something about it for TurboGrafx-16 in 1987 Hu6502 http://shu.emuunlim.com/download/pcedocs/pce_cpu.html

Transfer Alternate Increment (TAI), Transfer Increment Alternate (TIA), Transfer Decrement Decrement (TDD), Transfer Increment Increment (TII) - pretty much x86 'rep movsb', except not great at 6 cycles per byte (~160KB/s). For contrast 5 years older 80286 already did 'rep movsw' at 2 cycles per byte. 6 years later Pentium did 'rep movsd' at 4 bytes per cycle. Nowadays Cannonlake can do 'rep movsb' full cachelines at a time at full cache/memory controller speed.

[JPLeRouzic → rasz]

I think there are tricks to rewrite the microcode on Pentium, does similar tricks exist for 80286, 386 or 68K?

It would be fun to reconfigure one as a high speed 6502.