First 10G was 4x3.25G SerDes, so 4 traces to route on the board to the switch chip. There is some overhead in the signaling so you get 10G. If you plugged in a 1G, it just used one lane. Move to 40G, each lanes speed went up, 12G IIRC. At this point there was room for MAC/PHY so you go break each out to 4x10G. 256 traces to route to switch ASIC. Board routing is black magic. PHYless (no separate physical PHY chip required each set of 4 traces to be the same length down to the nm). Arista 7050 was first switch that shipped this. First 100G was 10 lanes, but lots of traces so smaller number of ports. Then they got the lanes up to 28G so you got 100G port for 4 lanes again, or 4x25G. So paired with MAC/PHY you could get 4x25G, 2x50, etc. and so on and so on as the speeds on the SerDes goes up. This is a simplified write up but mostly correct.
https://en.m.wikipedia.org/wiki/SerDes https://en.m.wikipedia.org/wiki/XAUI
First 10G was 4x3.25G SerDes, so 4 traces to route on the board to the switch chip. There is some overhead in the signaling so you get 10G. If you plugged in a 1G, it just used one lane. Move to 40G, each lanes speed went up, 12G IIRC. At this point there was room for MAC/PHY so you go break each out to 4x10G. 256 traces to route to switch ASIC. Board routing is black magic. PHYless (no separate physical PHY chip required each set of 4 traces to be the same length down to the nm). Arista 7050 was first switch that shipped this. First 100G was 10 lanes, but lots of traces so smaller number of ports. Then they got the lanes up to 28G so you got 100G port for 4 lanes again, or 4x25G. So paired with MAC/PHY you could get 4x25G, 2x50, etc. and so on and so on as the speeds on the SerDes goes up. This is a simplified write up but mostly correct.